Leakage Current in Sub-Micrometer CMOS Gates
نویسندگان
چکیده
Static power consumption is nowadays a crucial design parameter in digital circuits due to emergent mobile products. Leakage currents, the main responsible for static power dissipation during idle mode, are increasing dramatically in sub-100nm processes. Subthershold leakage rises due to threshold voltage scaling while gate leakage current increases due to scaling of oxide thickness. It means the static power dissipation should be considered as soon as possible in the design flow. Leakage mechanisms and reduction techniques will be reviewed, providing a minimum background about this issue.
منابع مشابه
Leakage Current Modeling in Sub - micrometer CMOS Complex Gates
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